UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 1655

4.1i UNISIMS, SIMPRIMS - How is the "$recovery" system task used in Block SelectRAM+ models?

Description

Keywords: Verilog, $recovery, Block, SelectRAM

Urgency: Standard

General Description:
How is the "$recovery" system task used in block SelectRAM+ models?

解决方案

The "$recovery" system task specifies a time constraint between an asynchronous control signal and a clock signal (e.g., between clearbar and the clock for a flip-flop). A violation occurs when a change to the signal occurs within the specified time constraint.

The $recovery system task has the following syntax format:

$recovery(<control_event>, <clk_event>, <recovery_limit>{, <notifier>});

<control_event>
An asynchronous control signal; this normally has an edge identifier associated with it, which indicates the transition that corresponds to the release from the active state.

<clk_event>
Clock (flip-flops) or gate (latches) signal; this, normally has an edge identifier to indicate the active edge of the clock or the closing edge of the gate.

The $recovery system task is used to check for one of two dual-port block RAM conflicts:

- If both ports write to the same memory cell simultaneously, violating the clock-to-setup requirement, the data stored will be invalid.

- If one port attempts to read from the same memory cell to which the other is simultaneously writing (also violating the clock setup requirement) the write will be successful, but the data read will be invalid.
AR# 1655
创建日期 08/31/2007
Last Updated 08/26/2003
状态 Archive
Type ??????