AR# 1659: XC4000E/EX/XL/XLT/XV: M1- TBUF net Delay 4000EX - Effect of the Pullup.
XC4000E/EX/XL/XLT/XV: M1- TBUF net Delay 4000EX - Effect of the Pullup.
Keywords: pullup, long line, TBUF, 4000EX
How does the internal 4000ex pullup modify the TBUF net delay?
Adding pullups will only help timing if the only thing "driving" the longline high is the pullups themselves (e.g. wired functions like WANDs). In these cases, adding a second pullup where there was only one before will improve the L->H transition by a quite a bit. Adding a third will only give a smaller improvement, and other effects like power dissipation come into play. Adding pullups to configurations where the tbufs are always actively driving high and low has only a marginal impact on the L->H transition, and can actually hurt the H->L transition.
On a more general note, the nature of the longline nets in the EX devices is somewhat different than in the E family. The quadlines, not the longlines, are generally the fastest routing resource. The advantages of using tbufs to efficiently implement things like wide muxes, bidirectional buses, and wired functions remains. This has been a strong advantage for Xilinx