When I run an SPI4.2 on a Virtex-II device, the RDCLK DCM loses lock, or DIP4 errors are reported. Some devices (boards) do not exhibit this behavior while others do.
The Phase Shift range of the DCM has been characterized as suggested in (Xilinx Answer 16112), but the design does not work consistently from board to board. Please see (Xilinx Answer 16112) for more details.
NOTE: This behavior presents itself only in the 4.0 and 5.0 versions of the SPI-4.2 core using the DCM in variable phase shift mode.
This behavior occurs because the RDCLK signal is loosing lock on the DCM.
Users should upgrade to the SPI-4.2 (PL4) 5.1 or later version of the core, as this behavior does not occur in the 5.1 or v5.2 versions of the SPI-4.2 core.
(NOTE: SPI 4.2 V5.2 requires ISE 5.1.03 or later software.)
If you absolutely cannot upgrade to the latest version, you can use the BitGen "Centered" option.
bitgen -g Centered_x0y0:0 design.ncd
Please see (Xilinx Answer 15130) for more information regarding this BitGen option.
To use the BitGen option above, you must specify the DCM site that your PL4 sink core is using. (The example above assumes DCM site x0y0.)
To determine the DCM site being used in your design:
1. Check your UCF file under the "Constrain the DCMs and associated BUFGMUXes" section. Look for an instance name that begins with "pl4_snk_top0/pl4_snk_clk0/...../rdclk_dcm0" LOC = DCM_x#y#. ("x#y#" indicates the DCM site.)
2. Open your routed NCD file using FPGA_Editor and locate the DCM site for "pl4_snk_top0/pl4_snk_clk0/...../rdclk_dcm0".
NOTE: You must be using fixed static alignment, as automatic static alignment is not supported. Please see (Xilinx Answer 12420) for other PL4-related known issues.