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XC5200/XC4000E/EX/XL/XV: How flip-flop initial states are determined for FPGAs.
4000, 4000E, 4000EX, XC4000XL, XC4000XV. devices only:
The initial state of a CLB Flip Flop after powerup, and after
deactivating the Global Set/Reset signal, is determined by the
library symbol that is used to instantiate the flip flop.
The initial state of CLB flip flops after powerup, and after
deactivating the Global Reset signal, is always reset, but it
is possible to use a library macro symbol which inverts the input
and output of the flop so that the flop (with inverter logic)
acts as asynchronously set flip flop after powerup and after
deactivating the Global Reset signal.
4000, 4000E, 4000EX devices:
There are two CLB flip flop primitives the FDCE and FDPE,
all other CLB flip flops are macros which utilize one of these
flip flop primitatives at a lower level.
All CLB flops that use the FDCE primitive will be in a
reset (0) state after powerup and after deactivating the Global
All CLB flops that use the FDPE primitive will be in a
set (1) state after powerup and after deactivating the Global
5200 devices only:
The 5200 devices behave just like the 4000 family of devices,
the only real difference is that the FDPE in the 5200 family is
a macro, which utilizes a FDCE and two inverters. Therefore
eventhough all flip flops in the 5200 devices are
asynchronously reset flops, you can get a set
behavior by utilizing a macro that uses the FDPE library symbol.
Xilinx has several "Bussed" Flip Flop macros, but all of
these macros will come up in a predefined state of all reset or
all set (the state is depenedent on the primitive flip flop
that the macro uses).
In order to get a "bussed" flip flop macro to come up in a
specific state, other than all set or all reset, the user will
need to create there own macro. When creating the Flip Flop
macro follow the guidelines in the previous resolution (ie.
use a FDCE flop for all reset flops and a FDPE all set flops)