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AR# 16829

Virtex and Spartan FPGAs - How does the JTAG JPROGRAM instruction work?

描述

Beginning with the Virtex-II generation of Virtex FPGAs, and beginning with the Spartan-3 generation of Spartan FPGAs, a JTAG instruction called JPROGRAM was introduced. This instruction has the same effect as toggling the external dedicated PROG_B pin on the FPGA, and is used to clear the FPGAs configuration memory before loading in a new bitstream.

Are there any issues that I need to be aware of when using the JPROGRAM instruction in an SVF/XSVF/ACE (JTAG) file?

Once JPROGRAM is issued, how do I know when the device has finished clearing configuration memory?

When using JTAG, is it possible to begin configuring the device if it has not finished clearing configuration memory?

For more FPGA Device Specific Issues and other Configuration Related Articles, see (Xilinx Answer 34104).

解决方案

Are there any issues that I need to be aware of when using the JPROGRAM instruction in an SVF/XSVF/ACE (JTAG) file?

If the mode pins of the FPGA are set for configuration from a non-JTAG configuration source (such as an onboard PROM), the JPROGRAM instruction must be followed by a CFG_IN instruction (used to shift in the bitstream) to keep the configuration source locked to JTAG. Since loading the JPROGRAM instruction is equivalent to toggling the PROG_B pin, if the JPROGRAM instruction is not followed by a CFG_IN instruction, the FPGA will attempt to initiate configuration based on the mode pin settings.

Sequences which will release the JTAG control over configuration include:

- Returning to the TEST-LOGIC-RESET tap state after the JPROGRAM instruction (TEST-LOGIC-RESET reloads the default IDCODE instruction)

- Loading instructions other than CFG_IN after the JPROGRAM instruction (for example, - IDCODE, USERCODE, or BYPASS)

Once JPROGRAM is issued, how do I know when the device has finished clearing configuration memory?

Using JTAG, you can use either of the following methods to determine if the FPGA has finished clearing configuration memory:

1. Shift out the INSTRUCTION_CAPTURE register and check the bit which indicates "house-cleaning is complete" (see the FPGAs BSDL for bit descriptions). The INSTRUCTION_CAPTURE register can be polled by returning to the JTAG TAPs CAPTURE-IR state before reloading the CFG_IN instruction. As the CFG_IN instruction is shifted into the device, the new INSTRUCTION_CAPTURE register value is shifted out on TDO, while in the JTAG TAPs SHIFT-IR state. See any JTAG documentation for more information on reading the INSTRUCTION_CAPTURE register.

2. Read the complete device STATUS register using a CFG_IN/CFG_OUT instruction sequence, and check to see if the INIT bit is High. For more information on reading the FPGAs internal STATUS register, see the Virtex User Guides, or for Spartan, see XAPP452:

http://www.xilinx.com/support/documentation/application_notes/xapp452.pdf

When using JTAG, is it possible to begin configuring the device if it has not finished clearing configuration memory?

No. If the device has not finished clearing configuration memory, new configuration instructions will be ignored. As the SVF format does not support looping instructions until a status is met, it is possible to start sending the new bitstream to the device before the device is ready. In order to guarantee that the device has completed clearing configuration memory and is ready to receive the bitstream, after replacing the JPROG_B instruction with a CFG_IN instruction, the programmer should wait in RUN-TEST-IDLE for the maximum clearing configuration memory time required for the FPGA (See the Tpl specification in the FPGA data sheets).

Example of a pseudo-SVF sequence:

SIR TDI (jprogram)

SIR TDI (cfg_in)

RUNTEST max_Tpl_time

SIR TDI (cfg_in)

SDR TDI (...the configuration bitstream goes here...)

To issue JPROGRAM within iMPACT, use the Debug Mode, following the steps in the example below:

1. Open iMPACT.

2. Initialize chain and locate the BSDL files for the devices in the chain. For Xilinx devices, the BSDL files are located in the $XILINX/<device type>/data directory and have a .bsd extension.

3. Search for BYPASS (or HIGHZ) instruction for any devices that will stay in their current state. The BYPASS instruction for a IEEE1149.1 compliant device will always be all ones.

4. Search for JPROGRAM for any Xilinx FPGAs that are to be reset with the JPROGRAM command.

5. Proceed to File -> Start Debug Chain in iMPACT.

6. In the Debug Chain window, press the Test Logic Reset (TLR) button to ensure that the devices in the chain are in a known state.

7. In the Debug Chain window, paste into the Scan IR field the concatonated instruction shift for the entire device chain, with the BYPASS (or HIGHZ) instruction loaded for any device which is not receiving the JPROGRAM instruction.

For example, a chain consisting of an XCF01S (IR length of 8), an XC3S50 (IR length of 6), an XCF08P (IR length of 8), and an XC5VLX30 (IR length of 10), enter the following string in the Scan IR field:

1111111100101111111111111111111111001011

Where "11111111" is the BYPASS instruction for the XCF01S, '001011" is the JPROGRAM for the XC3S50 ,"1111111111111111" is the BYPASS instruction for the XCF08P, and "1111001011" is the JPROGRAM for the XC5VLX30.

8. In the Debug Chain window click Execute, to shift in the Scan IR value. (In the above example, both FPGAs would be reset simultaneously.)

9. In the Debug Chain window, press the Test Logic Reset (TLR) button to reset the JTAG instruction register to the default value (removing the JPROGRAM instruction). At this point, the FPGA will attempt configuration from the source selected by the configuration mode pins. If the FPGA is in a Master mode, the CCLK will start toggling.

AR# 16829
日期 03/17/2010
状态 Active
Type ??????
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