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AR# 1686

5.x XACT FPGA - Asynchronous design which worked on older devices may fail in newer devices


The design has been working with a particular lot of Xilinx parts, but when a new lot of parts are used (same part/speed), the design fails. What happened?

This usually indicates asynchronous design practices. For instance, at some point in the design, a circuit might depend on a path being *slow*, to prevent a race condition. This may indeed work sometimes, but you should realize that Xilinx parts are periodically fab'd on a faster process, so you cannot assume a particular parameter will not speed up later on.

Even if you have the exact same speed grade, one part may still
be significantly faster than another, since Xilinx guarantees
worst-case parameters only.

Examples of problematic design practices include gated clocks
(which introduces significant delay to the clock net), flip-flops with the asynchronous reset/preset driven by internal logic (flip-flop's state could be reset before clock edge in one part, after clock edge in another), combinatorial loops (potential race condition, if loop's state is clocked before feedback is completed in one part, and after feedback has completed in another).


You can run a DRC check to report on possible asynchronous
paths in your design by going into "xde" and selecting
Programs > DRC -Informational.

The real solution is to make the design fully synchronous,if possible. You can, of course, add more delay to paths that need
it, but that is obviously an inferior solution since you will likely have to deal with this problem again when the parts become faster.
AR# 1686
日期 03/22/2000
状态 Archive
Type ??????