AR# 16896


LogiCORE PCI - Bit 3 of Status Register, the interrupt status bit, or CSR[19] is inverted from its correct value. It is a '1' when it should be a '0' and vice versa


General Description:

The Interrupt Status bit, which is bit 3 of the Status register or CSR bit 19, is behaving opposite of what it should. This bit reflects the state of the interrupt in the device, and it should be 1 if the device is asserting the interrupt and 0 otherwise. However, it is a 0 when the core is asserting the interrupt and a 1 otherwise.


This issue has been corrected. The first build showing this fix is release 3.106.

AR# 16896
日期 12/15/2012
状态 Active
Type 综合文章
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