AR# 16950


LogiCORE SPI-4.2 (POS-PHY L4) v5.2.2 - Design does not meet timing constraints when the 2v6000 dynamic alignment netlist is used


General Description:

My design does not meet timing constraints or does not function properly in the timing simulation or device when I use the 2v6000 dynamic alignment netlist.


This problem affects the 2v6000 files that were delivered in the v.5.2.1 and v5.2.2 archive (zip and tar.gz) files.

This problem has been fixed in the v5.2.3 archive files, which are available in the SPI-4.2 lounge on the Xilinx Web site at:

AR# 16950
日期 05/03/2010
状态 Archive
Type 综合文章
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