AR# 16953: 9.1i PrimeTime/NetGen - How do I get the files for PrimeTime from the Xilinx tools?
9.1i PrimeTime/NetGen - How do I get the files for PrimeTime from the Xilinx tools?
keywords: primetime, files, tools
How do Iget the files from PrimeTime from the Xilinx Tools?
Preparing PrimeTime Compatible files
This section describes the generation of design?s files for PrimeTime.
Creating PrimeTime compatible Verilog Gate Level Netlist and SDF
Implement the design through NGDBUILD, MAP and PAR. Consult the PAR report to ensure a successful run and then to create a PrimeTime specific simulation netlist: 1. Set the environmental variables setenv XIL_ANNO_DISABLE_GSUH 1 setenv XIL_ANNO_REMOVE_UNUSED_DELAY 2. Run ngdanno -p (to use voltage and temp. in the PCF file to de-rate the delays in the sdf file) 3. Run ngd2ver (to generate Verilog netlist and associated SDF file) The Verilog netlist contains LUTs, flip-flops, BRAM and other components from the SIMPRIMS library. In the Verilog netlist, functionality of LUT elements are specified with ?INIT? strings using Verilog ?defparam? construct. Since PrimeTime only accepts synthesizable Verilog, we must comment out all the simulation constructs including the ?defparm? in the Verilog netlist. Consequently, LUT elements appear as black boxes to PrimeTime. However, PrimeTime needs to understand the functionality of the LUT elements for operations such as case analysis, identifying logical false paths, and justifying false paths. Since the LUT function can be represented with a configured MUX function, the LUT elements in the netlist have to be replaced with configured MUX elements that reflect their functions. This required 3 MUX elements for 3 types of LUT elements that may appear in the Verilog netlist. These 3 MUX elements are added to the PrimeTime SIMPRIMS library. They are X_LUT2MUX4, X_LUT3MUX8 and X_LUT4MUX16 elements replacing 2-input, 3-input and 4-input LUT elements in the simulation netlist. ISE 4.2i onwards, MAP primarily uses 4-input LUT element to implement the combinatorial functions in the design, therefore the simulation netlist has predominantly 4-input LUT elements that will be replaced by X_LUT4MUX16 in PrimeTime netlist. The xilinx2primetime program reads the Verilog simulation netlist specific for PrimeTime and corresponding SDF file that were previously created, and generates PrimeTime compatible Verilog and SDF files containing X_LUT4MUX16 elements, enabling PrimeTime to recognize the functionality of the LUT elements in the netlist.
Note: X_LUT4MUX16 element does not exist in the silicon since it represents the LUT functionality to PrimeTime.
To enable accurate timing analysis of the netlist that is annotated with the SDF file generated by xilinx2primetime, PrimeTime must be properly constrained using the same constraints that were used to drive place and route in ISE. The PCF file drives PAR and contains timing constraints in Xilinx constraint format. Since PrimeTime only accepts SDC formatted timing constraints, xilinx2primetime converts relevant timing constraints in the PCF file to their equivalent SDC constraints. When translating timing constraints between two different formats, sometimes constraints do not map one-to-one. Therefore, some PCF constraints may require manual translation to SDC. These are reported in the x2p.log file created by xilinx2primetime.