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AR# 16989

3.2 EDK - PlatGen creates an incorrect system.vhd or system.v file


General Description: 

When the following syntax is used in the MHS file, and the design is NOT the top-level, PlatGen generates an incorrect system.vhd or system.v file, which fails in synthesis or simulation. 


PORT leds = leds_s, DIR = INOUT, VEC = [3:0] 


The system.vhd/.v file fails to include a signal/wire declaration for "leds_s".


You can easily resolve this issue by using the same port and signal name: 


PORT leds = leds , DIR=IO, VEC=[3:0]

AR# 16989
日期 05/15/2014
状态 Archive
Type 综合文章