AR# 17023


XST - "ERROR:Xst:797 - file_name line xx: unsupported Clock statement"


Keywords: clk'event, ISE, 5.2, dual, edge, CoolRunner

Urgency: Standard

General Description:
What kinds of clock statements are supported?


XST does not support the use of a complex condition check inside a process block in VHDL.

For example, the following code will result in an error:

if (clk1'event or clk1 = '1') or (clk2'event or clk2 = '1') then

When inferring hardware from HDL, it is important to keep in mind the type of hardware you want.

The XST User Guide is available at:
It contains basic templates for the various FPGA/CPLD hardware that can be inferred with HDL code. If you model your HDL code after the templates provided, you will infer the desired hardware.

However, the error message in the title of this solution will also appear when attempting to infer a dual-edge triggered flip-flop:

if clk'event then

in any device other than a CoolRunner-II, as the CoolRunner-II is the only device that has dual-edge triggered flip-flops.
AR# 17023
日期 10/20/2005
状态 Active
Type 综合文章
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