General Description:
What is the minimum reset pulse width for Xilinx CPLDs?
XC9500/XL/XV
The minimum reset pulse width is equal to the pad-to-pad delay value (Tpd). This value is available in the device data sheets:
CoolRunner XPLA3, CoolRunner-II
The minimum reset pulse width is equal to the P-term clock pulse width (Tplh for XPLA3, and Tpcw for CR-II). This value is available in the device data sheets:
http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?category=/Data+Sheets/CPLD+Device+Families&iLanguageID=1
AR# 1707 | |
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日期 | 12/15/2012 |
状态 | Active |
Type | 综合文章 |