AR# 17130


5.2i CORE Generator/Ten Gigabit Ethernet MAC v3.0 - Release Notes


Keywords: F_IP3, FIP3, 10GMAC, MAC, 10GEMAC, gigabit, ten gigabit, ethernet, FIP2, COREGen, XAUI, XGMII, Virtex-II Pro, Virtex-II, networking, connectivity

Urgency: Standard

General Description:
This Answer Record contains the Ten Gigabit Ethernet MAC - F_IP3 Release Notes


Ten Gigabit Ethernet MAC

New Features in v3.0

- Core is customizable through the 5.2i CORE Generator GUI.
- Added support for new top-level HDL wrappers (VHDL and Verilog) containing the clock management logic and all I/Os for the core. You can manually customize this wrapper if needed.
- Added an option to generate the core without the Host Management Interface and substitute a configuration vector in its place.
- Added support for the XAUI interface in Virtex-II Pro -6 speed grade.
- Added configurable fault generation for asymmetric applications.

Bug Fixes in v3.0

- Reliability is improved for a potential metastability condition involving the handling of ENPCOMMAALIGN /ENMCOMMAALIGN (XAUI configuration).
- XAUI configuration now uses BREFCLK and BREFCLK2.
- Clock domain crossing reliability is improved in the statistics block.
- A problem with the flow control logic related to making a new frame transmit at the same time as a zero pause frame is received is fixed. The problem would cause the core to completely stop transmitting frames, and it was necessary to reset the core in order for it to work again. This edge-case condition would appear after a short time if the core was receiving a large number of pause frames.
- In the data sheet, the descriptions of Flow Control Bits 29 and 30 are corrected (the definitions were swapped).

Known Issues
- When maximum length frames are combined with minimum length inter-frame gaps, TX_ACK incorrectly pulses for two cycles and the frame is corrupted. To work around this issue, download the patch in (Xilinx Answer 17559).
- For certain CORE Generator modules, user-specified component names exceeding 24 characters in length may cause CORE Generator to hang. To work around this issue, limit user-specified component names for CORE Generator cores to 24 or fewer characters. In addition, limit the path to the project to 12 characters. For more information, please see (Xilinx Answer 17164).
AR# 17130
日期 08/31/2006
状态 Archive
Type 综合文章
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