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AR# 17183

5.2i Speed Files - Why did the I/O output adjustment values in timing report change in ISE 5.2i? (1.114+)


Urgency: Hot

General Description:

In ISE 5.2i, the I/O output adjustment values in the speed files changed. For example, ISE 5.1i included the following I/O adjustment values:

LVDCI_33 -> 1907 ps

LVDS_25 -> -1277 ps

In ISE 5.2i, these numbers were changed to the following:

LVDCI_33 -> 739 ps

LVDS_25 -> -317 ps

Some of the current IOB adjustments are better, but others are worse. Why did this change occur?


In ISE 5.2i , the Virtex-II speed files are updated to version 1.114. Please see (Xilinx Answer 12201) for a table of speed files versions and software releases.

In the previous release of the speed files, the I/O timing parameters were characterized using a 35pF load. These files are now characterized using a 0pF load to make them consistent with the other device families. The current numbers in the speed files are now consistent with the current loading specification of 0pF, 50 Ohms.

Why did these numbers change?

The software processes different I/O standards by first calculating a delay (i.e., Tioop) for a baseline standard (for Virtex-II, it is LVTTL_F12) and then adjusting it for the I/O standard used to program the external pin. The measurements are performed under specified loading conditions. For more information on how these measurements are obtained, please see Solution 3 below.

Historically, the specification for the loading on the pins was 35pF, but because Virtex-II supported many different standards, each with its own specification, the loading on the test equipment was different for different standards. These characterizations were reflected in version 1.100 of the speed files.

Xilinx then decided to make all of the specifications uniform at 35pF load. Essentially, this changed the specification for many of the I/O standards, some of which were 0pF, others were 10pF, and so on. This change caused many adjustments to change radically because relative to the baseline of LVTTL_F12, the clock-to-out (Tiockp) for some standards was much worse. However, devices with a stronger driver were able to handle the extra load more easily and looked better by comparison at 35pF. These numbers were introduced in version 1.105 of the speed files and remained through version 1.113.

Shortly after these changes were released, Xilinx decided that (based on the quick transition ability of today's circuits) a transmission line model with 0pFd and 50 Ohm loading was more appropriate. These numbers were reflected in version 1.114 of the speed files released with 5.2i. It is important to note that none of these speed files changes occurred because of a change in silicon performance.

Why did some numbers get better and some get worse?

The characterization performed for version 1.105 through version 1.113 of the speed files (35pf load) calculated the baseline number (LVTTL_F12) incorrectly. Xilinx used the baseline number characterized with a 35pF load, but it was actually characterized using a 0pF load. As a result, in all of these speed files versions, the baseline clock-to-out delay never changed. The I/O adjustments changed because they were characterized using the 35pF load. Consequently, the I/O adjustment numbers were skewed because of the incorrect baseline.

For example in version 1.113, the IOB adjustment for LVDCI_33 was 1907 ps and LVDS_25 was -1277 ps. Actually, both delays should have been slower but were incorrect because of the inaccurate baseline. In version 1.114, the IOB adjustment for LVDCI_33 was 739 ps and LVDS_225 was -317 ps. In this case, the LVDS_25 adjustment was slower and the LVDCI_33 adjustment was faster. If these delays were incorrect in version 1.105 through 1.113 of the speed files, then the IOB adjustment delays for both LVDCI_33 and LVDS_22 in version 1.114 would have been faster. Since the delays were not accurate in version 1.105 through 1.113, some delays in version 1.114 appear to have become worse. The LVDS driver, which is a stronger driver, appeared better in version 1.113 because of the inaccurate baseline and it was able to handle the 35 pF load better than weaker drivers. However, since the baseline was inaccurate, the adjustment seems to be slower with the 0 pF load. Figure 1 below shows how the IOB adjustment numbers changed from previous versions and how the numbers should have changed. The data in version 1.114 is correct and these numbers are not expected to change.

Figure 1
Figure 1

What impact will this have?

Delays associated with certain I/O standards changed. Many are better, but as a general rule, the faster, stronger drivers, (e.g., LVDS or HSTL) are impacted the most. This change affects the clock-to-out times, but not the setup/hold times unless different standards are used for the clock and data pins. It is important to note that none of these changes occurred because of a change in silicon performance. These changes are strictly a result of changes to specifications. If you previously met timing on your board, you will continue to meet timing.

Will I have to change my OFFSET constraint?

No, if your design requires an OFFSET OUT of 3 ns then it stays the same. However, due to the I/O standard that you are using, you may need to verify that it will meet timing. You can use IBIS simulations to help with the verification. Please see Solution 3 below for more information on how to set up an IBIS simulation.

The following IOB adjustment numbers are now slower:

LVTTL Slow 16

LVTTL Slow 24

LVTTL Fast 16

LVTTL Fast 24

LVCMOS15 Fast 12

LVCMOS15 Fast 16

LVCMOS18 Fast 12

LVCMOS18 Fast 16

LVCMOS25 Slow 16

LVCMOS25 Slow 24

LVCMOS25 Fast 12

LVCMOS25 Fast 16

LVCMOS25 Fast 24

LVCMOS33 Slow 12

LVCMOS33 Slow 16

LVCMOS33 Slow 24

LVCMOS33 Fast 12

LVCMOS33 Fast 16

LVCMOS33 Fast 24













































I/O standard adjustments are measured using a Tektronix P6245 TDS500/600 probe (< 1 pf) across approximately four inches of FR4 micro strip transmission line. The propagation delay for the four inches of FR4 is characterized separately and subtracted from the final measurement. I/O standard adjustment measurements are reflected in the IBIS model except where the IBIS format precludes it. The use of IBIS models results in a more accurate prediction of the propagation delay. You can use the following method to measure propagation delay:

1. Model the output in an IBIS simulation using the Generalized Test Setup shown in Figure 2.

2. Record the relative time to the VOH or VOL transition of interest; this is the baseline simulation.

3. Model the actual PCB traces (transmission lines) and actual loads from the appropriate IBIS models for the driven devices.

4. Record the results from the new simulation.

5. Compare with the baseline simulation. The increase or decrease in delay from the baseline simulation must be added or subtracted to the I/O Output Standard Adjustment value to predict the actual propagation delay.

Figure 2
Figure 2

You can download a free IBIS simulator from the following Web site:

AR# 17183
日期 11/06/2011
状态 Archive
Type 综合文章