We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 17184

8.2i Virtex-II MAP - Distributed RAM appears to waste an extra LUT for the SPO output that is not used


In my design, the "modified" single-port distributed RAM (RAM with dual-port addressing, but single-port output) uses two LUTs. If I am not using the outputs for a second LUT (which will end with an SP), why does this not get trimmed away?


If the SPO (single-port out) is unused, it is still necessary to use both LUTs. This occurs because even though the SPO LUT is not needed, it cannot be used for anything else as its address lines are bound to the DPO half.

If you want a true single-port distributed RAM, use the Language template and it will use one LUT, and dual-port will use two LUTs.

AR# 17184
日期 12/15/2012
状态 Active
Type 综合文章