AR# 17244


Virtex-II Pro, Virtex-4 - Four new I/O standards are available with a differential termination at the differential input pair


Keywords: terminated, LVDS, terminate, resistor, 100, ohms, DT, DIFF_TERM

Four I/O standards for Virtex-II Pro and Virtex-4 are available with a differential termination (DT) at the differential input pair. These standards enable true differential termination resistors for differential inputs for Virtex-II Pro and Virtex-4. They are not applicable to Virtex-II. The on-chip input differential termination in Virtex-II Pro and Virtex-4 provides major advantages over the external resistor or the DCI termination solution.

This support is available in the ISE 5.2i Service Pack 3.

For Virtex-II Pro, the I/O standards are as follows:


For Virtex-4, the attribute DIFF_TERM is available to enable DT in the same four I/O standards : LVDS_25, LVDSEXT_25, LDT_25, and ULVDS_25.

- If these I/O standards are applied to the output, the software errors out. Refer to (Xilinx Answer 14128) for more information.
- When these I/O standards are used with the IBUFGDS_DIFF_OUT input buffer, the termination is not enabled. This issue is fixed in 6.3i Service Pack 1.



Virtex-II Pro Device Support
Currently, all Virtex-II Pro production devices support differential termination.

However, for XC2VP7 and XC2VP20 devices, you must use a specific ordering code (SCD) to order devices with DT support. For device availability and ordering information, please contact your FAE or Xilinx sales office.

Background Information
In April 2003, the XC2VP7 and the XC2VP20 were the first devices built and qualified in the initial production circuit revision B, which did not support the Differential Termination feature. Subsequently, all other Virtex-II Pro devices went into production with Differential Termination support. The Differential Termination feature was later "added" to the XC2VP7 and XC2VP20 devices with circuit revision C. The circuit (mask) revision is the first letter of the three-letter code described below.

The three-letter code is located on line two of the package marking after the package type, for example:


On line two of the marking, "CGB" is the three-letter code, and "C" denotes that it is from the circuit (mask) revision C. Refer to (Xilinx Answer 1067) for more information on device marking.

Additionally, the device ordered with SCD will contain the 4-digit SCD # on line 4 following the speed grade; for example, -5C ####.

If you have Virtex-II Pro ES (marked on the package) devices or XC2VP7/XC2VP20 devices with no SCD marking, the following table shows the identifying code and its corresponding JTAG ID for all Virtex-II Pro devices with DT support.
Device support table
Device support table

- ALL 2VP30 and larger devices support DT.
- For 2VP4 and 2VP7 only, the circuit revision "C" marking and JTAG ID also identify devices supporting the DCIUpdateMode. See (Xilinx Answer 13012) for more information regarding DCIUpdateMode support. DCI is not the same as DT.
- For devices without DT support, the LVDS_25_DCI and LVDSEXT_25_DCI I/O standards can be used to provide on-chip LVDS input termination. The differences between DT and DCI are listed below. Refer to the Virtex-II Pro Data Sheets and User Guides for more information on DCI.

Data Sheets:

User Guides:

Instantiation Template and Termination Diagram
Refer to the Virtex-II Pro Data Sheets at:

For the termination diagram and the I/O banking/voltage compatibility, refer to the Virtex-II Pro Detailed Functional Description (Module 2) -> Functional Description: FPGA -> "Input/Output Block (IOBs)" and "On-Chip Differential Termination" sections.

For the instantiation template, refer to the Virtex-II Pro Platform FPGA User Guide at:

1. Select Virtex-II Pro under "FPGA Device Families" and select the Virtex-II Pro Platform FPGA User Guide.
2. Select Design Considerations -> LVDS I/O.


Virtex-4 Device Support
All Virtex-4 devices support DT.

Attribute and Termination Diagram
In Virtex-4, DT is enabled by attaching the DIFF_TERM attribute to IBUFDS/IBUFGDS instantiation.

Please refer to the Virtex-4 User Guide for more information on the attribute and termination diagram:

Select IO Resources -> Specific Guidelines for Virtex-4 IO Supported Standards -> Differential Termination: DIFF_TERM Attribute.


Design Guidelines
Unless otherwise noted, the following guidelines apply to Virtex-II Pro/X and Virtex-4.

Requirement to turn on the On-chip Input Differential Termination
The VCCO of the I/O bank must be connected to 2.5V to provide 100 ohms of effective termination. The differential termination I/O standard can be used only with a VCCO=2.5V +/- 5% for the bank in which it is used. This is an input-only standard. The differential termination I/O standard cannot be used in the bank with VCCO = 3.3V.

NOTE: Beginning in ISE 6.1i, this requirement is implemented in the software.

Advantages of On-chip Input Differential Termination over External Termination Solution
Because the on-chip termination is immediately before the input buffer, it completely eliminates the stub at the receiver and greatly improves signal integrity.

Advantages of On-chip Input Differential Termination over the DCI Termination Solution
- The DCI termination solution consumes static power due to DCI termination to VCCO/2. See (Xilinx Answer 15633) for LVDS_25_DCI power cost.
- The static power due to DCI is eliminated when on-chip differential termination is used.
- The on-chip DT at the input consumes no power as the current across the DT is from the transmitter and is sunk back into the transmitter. Consequently, this current does not add to the VCCO current (power).
- The DCI termination solution provides an input common mode voltage of VCCO/2, that is, 1.25V. Consequently, it does not support the LDT standard, which requires a lower Vicm (600 mV) voltage.
- Because the on-chip differential termination solution does not require VRN/VRP pins, it frees up the bank for other DCI requirements.

What will happen if I mistakenly layout LVDS_25_DT in a 3.3V VCCO bank? Will it damage the device?
Setting VCCO to 3.3V in the bank where DT I/O standards are used will not damage the device. When VCCO is at 3.3V, the impedance between P&N will be smaller. This impedance can be measured between P&N pins of the LVDS pair. However, Xilinx does not have characterization data for 3.3V. Our recommendation remains to use 2.5V VCCO for 100-ohm termination.

What is the accuracy of 100 ohm differential termination?
This number is available in HSPICE and IBIS model. In IBIS model, this is noted in the rterm_100 model. It is approximately 100 ohm +/- 20%.

What will happen if a bitstream using DT I/O standard is programmed on the device with no DT support?
This guideline does not apply to Virtex-4 or later (as all devices support differential termination).
In Virtex-II Pro devices with no DT support, if a bitstream using DT I/O standard is programmed,
the input will be programmed as I/O standard without DT. For example, if LVDS_25_DT is specified, the input will be programmed as LVDS_25. The termination must be provided externally for this input as it is when LVDS_25 is used. This will not affect any signaling.

See (Xilinx Answer 14178) for availability of IBIS and HSPICE models.

AR# 17244
日期 10/07/2008
状态 Active
Type 综合文章
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