We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 17276

LogiCORE Pipelined Divider v2.0 - Is the divider core available for Virtex-II Pro or Spartan-3?


Keywords: Virtex-II Pro, pipelined divider core, available, Spartan-3, COREGen, core, generator, divider, RPM

Urgency: Standard

General Description:
In the COREGen GUI, the Pipelined Divider core is not available for Virtex-II Pro and Spartan-3. Are there plans to offer this for these devices?


This has been fixed in the Pipelined Divider v3.0.

The FPGA fabric for the Virtex-II and Virtex-II Pro/Spartan-3 are similar. The fundamental difference between S-3 and V-II/Pro is the CLB having 2 normal slices (SliceM) and 2 non SRL16E/RAM16x1 (SliceL). As long as Relationally Placed Macros are not used, these differences have no effect on using the Virtex-II core in a Virtex-II Pro or a Spartan-3. To use the core for either Spartan-3 or Virtex-II Pro follow these steps:

1. Change the device for your ISE project to Virtex-II.
2. Select "Add a new Source" (to your ISE project) and select COREGen IP.
3. Run the COREGen GUI and generate the Pipelined Divider core.
4. Change the device for your ISE project back to Virtex-II Pro or Spartan-3.
5. Instantiate the core in your top-level source.
6. If the core needs to be re-parameterized, repeat steps 1-4.
7. Before implementing the design, ensure that RPMs are turned off.
(Some cores to not offer RPMs, so if you do not see this option in the core GUI then ignore step 7.)

NOTE: Since the RPMs must be turned off, the timing performance of the core might be adversely affected.
AR# 17276
日期 07/26/2007
状态 Archive
Type 综合文章