AR# 17277


MicroBlaze - How deep and wide is the instruction buffer and what is it used for ?


General Description: 

How wide and deep is the instruction buffer? What is the instruction buffer used for?


The instruction buffer is 32 bits wide and 16 bits deep since it is implemented with 32 SRL16s. However, only 4-5 of the words are used. The instruction buffer does not utilize any BRAM and improves the overall performance especially when the instruction cache is not enabled in MicroBlaze.  


You can think of the instruction buffer as a mini-cache. You can use it to store a few instructions so that multiple consecutive instructions can be accessed quickly. However, this does not help with branches; if a branch occurs, the instruction buffer is flushed because the remaining instructions are no longer useful. 


There are two benefits to using the instruction buffer: 

1. When MicroBlaze is executing a multi-clock cycle instruction, such as MUL or DIV, the instruction fetch can pre-fetch instructions to minimize bus latency when fetching over the OPB. When only running over the LMB, there is no advantage.  

2. It makes the implementation of the pipeline control much easier.  


Without the instruction buffer, the pipeline cannot be moved unless there is a new instruction coming in, and a new fetch cannot start unless it is known that the instruction can be used. For example, a DIV instruction takes 35 clock cycles. When running over just the LMB, a new fetch starts at clock cycle 33. However, when running over OPB, it depends on the OPB latency. This makes the pipeline handling extremely complex.  


With the instruction buffer, a fetch can happen if there is space in the buffer, independent of the current instruction. The pipeline can be moved as long as there are instructions in the buffer. The reason not all 16 positions in the buffer are used is because in practice there is normally a branch instruction after an average of 5-7 instructions, and for each branch, the instruction buffer is invalidated. Fetching too many instructions introduces unnecessary memory fetches on the bus and may stall other masters on the bus.

AR# 17277
日期 05/15/2014
状态 Archive
Type 综合文章
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