AR# 17369


5.2i CORE Generator / LogiCORE XAUI v3.0 - 'X's in back-annotated simulation when MDIO interface is implemented


Keywords: FIP4, COREGen, XAUI, Virtex-II Pro, MDIO, MDC, X, unknown

Urgency: Standard

General Description:
When performing back-annotated simulation of the XAUI v3.0 core with the optional MDIO interface implemented, 'X's occur in the simulation. Specifically, this occurs when MDC is not related to the USRCLK.


This can occur if the rising edge of MDC appears in the setup time with respect to USRCLK on the register that is used as the synchronizer. To resolve this problem, add the following lines to the .ucf file and re-implement:

INST "xaui_core/BU2/u0/management_1/mdc_rising" ASYNC_REG = "TRUE";
INST "xaui_core/BU2/u0/management_1/mdio_interface_1/mdio_in_reg" ASYNC_REG = "TRUE";
AR# 17369
日期 08/31/2006
状态 Archive
Type 综合文章
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