The ".do" files generated when "Create testbench" is used have the wrong compilation command for Verilog black boxes.
The ."do" files contain "vcom -93 myfile.v" when instead they should have "vlog myfile.v".
This causes errors in compilation in ModelSim.
To work around this issue, manually edit the compilation line for Verilog files. Remove "vcom -93" and replace with "vlog".
This has been fixed in the software as of System Generator for DSP v6.1.