We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 174

SYNOPSYS/XSI: Using an Input Latch (ILD_1) with No Delay


The xc4000 input latch can be configured to have different delay options, using the
fast and nodelay properties. How are these attached in Synopsys?


The standard input latch (ILD_1) available in the Xilinx-Synopsys interface library includes a built-in delay which forces the input latch to have a zero hold time. This slows down the input latch.
In order to use an input latch without the built-in delay, Instantiate an ILD_1F primitive instead of an ILD_1 (INIT=Reset) or ILDI_1F instead of an ILDI_1 (INIT=Set).

Note that these input latches without a built in delay must be instantiated as they cannot
be automatically inferred.
See the Synopsys (XSI) for FPGAs Interface/Tutorial Guide, Appendix B, for more

AR# 174
日期 11/08/2004
状态 Archive
Type 综合文章