We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 17499

8.1i PACE - The MSB and LSB bus order are not honored in the HDL file


Keywords: MSB, LSB, order

When I create a new HDL-based design containing buses, LSB is always the smaller number and MSB is always the larger number. I cannot create a bus that is bus1[3:0], because it will always be written as bus1[0:3]. When bus groups are displayed, however, they do show the correct order.


You can work around this issue by changing the order of the bus notation in the HDL file.

This should be fixed in the next major release of the design tools.
AR# 17499
日期 06/17/2008
状态 Archive
Type 综合文章