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AR# 17627

3.1 SP1 System Generator for DSP - Why are the constant values sometimes incorrect when SysGen generates the VHDL for a MCode block?

描述

General Description: 

When generating a SysGen design which instantiates multiple instantiations of a Simulink MCode block containing constant values, the VHDL files that are generated for the MCode block contain incorrect values for the constant.

解决方案

This has been fixed in System Generator 3.1 service pack 1 

 

http://www.xilinx.com/products/software/sysgen/sg_intro.htm

AR# 17627
日期 05/15/2014
状态 Archive
Type 综合文章
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