This answer record contains a list of all known issues for SPI-4.2, also known as POS-PHY Level 4 (PL4) v5.2 and v5.2.3 (patch). The list is divided into the following sections:
- Constraints and Implementation
- Other Helpful Answer Records
v5.2 PL4 KNOWN ISSUES
Constraints and Implementation:
1. PL4 v5.2 release is fully tested and supported to work with ISE 5.1i SP3, 5.1i IP Update 1, and ISE 5.2i.
If you are using ISE 4.2i, please see (Xilinx Answer 16545). If you are using a Virtex-II Pro device with status bits set to LVTTL, you must use ISE 5.2i.
2. An error is reported when IP Update 2 (F_IP2) is installed. When I generate SPI-4.2 (PL4) v5.2 files with CORE Generator 5.2i with the IP Update 2 installed, an error is reported during the simulation of the FIFO loop-back example in VHDL. Please see (Xilinx Answer 17019) for more information.
3. Does the SPI-4.2 (PL4) Core have a required startup sequence or reset procedure? Please see (Xilinx Answer 16176).
4. When I attempt to place BUFGMUX or BUFG in a certain location, the following error is reported in PAR:
"ERROR:Place:1897 - A global clock component <pl4_src_top0/pl4_src_clk0/tsclk_bufg0> configured as a selectable mux is placed in site BUFGMUX3S."
Please see (Xilinx Answer 15673).
5. When I generate a POS-PHY Level-4 (PL4) v5.2 Core for an XC2V2000FG676-5 device, CORE Generator reports an error. Please see (Xilinx Answer 16539).
6. On a PC running ISE 5.1i SP3 MAP with a PL4 Core, the following fatal error is reported:
"FATAL_ERROR: Pack:pktbafirewall.c: 138:1.1 - Failed to create device helper. Process will terminate."
Please see (Xilinx Answer 16556).
7. When I run the ISE 5.1i Place and Route tool (PAR) with an SPI-4.2 (PL4) Core, many timing errors are reported. Please see (Xilinx Answer 16540).
8. When an SPI-4.2 (PL4) Core is generated through CORE Generator, the following errors are reported:
"ERROR:Failure to create .sym symbol file. Cannot post process ASY symbol file. File C:\test\4_2i\pl4_core.asy does not exist."
"ERROR: Did not generate ISE symbol file for core <pl4_core>"
Please see (Xilinx Answer 15493).
9. My design does not meet timing constraints or does not function properly in the timing simulation or device when I use the 2v6000 dynamic alignment netlist. Please see (Xilinx Answer 16950).
1. If you are using ISE 5.2i or ISE 5.2i with Service Pack 1 and performing VHDL simulation, please install UniSim and SimPrim patches. The patches are needed to simulate the DCM module that is implemented in the SPI-4.2 Core. Please see (Xilinx Answer 16847).
2. When FIFO loop-back example VHDL simulation files are compiled using IP Update 2, the compiler reports errors for the pl4_snk_top.vhd and pl4_src_top.vhd files. Please see (Xilinx Answer 17019).
3. When I simulate a SPI-4.2 (PL4) source Core, glitches occur on TDat and TCtl. This is visible on gate-level simulation as well as in timing simulation. Please see (Xilinx Answer 15579).
4. Simulation of the SPI-4.2 (PL4) Core using dynamic alignment requires timing simulation to properly simulate the dynamic alignment per-bit de-skew capabilities of the Sink Core. Please see (Xilinx Answer 15436).
5. When I simulate an SPI-4.2 (PL4) Core using NC-Verilog (by Cadence) or VCS (by Synopsys), unusual and inconsistent behaviors occur. Please see (Xilinx Answer 15578).
1. When Fixed Static Alignment is used, it is necessary to determine the best DCM setting (PHASE SHIFT) to ensure that the target system contains the maximum system margin and performs across voltage, temperature, and process (multiple chips) variations. Please see (Xilinx Answer 16112).
2. An SPI-4.2 (PL4) Sink Core with dynamic alignment fails to activate PhaseAlignComplete, goes out of sync, or reports a DIP4 error. Please see (Xilinx Answer 15442).
Other Helpful Answer Records:
1. What is the power consumption of the v5.2 SPI-4.2 (PL4) Core? Please see (Xilinx Answer 16034).
2. Is there a description of error and control signals in addition to the information provided in the SPI-4.2 (PL4) Data Sheet? Please see (Xilinx Answer 14968).
3. How do I edit the SPI-4.2 (PL4) UCF file so that the TSClk is skewed by 180 degrees in the DCM? Please see (Xilinx Answer 15500).