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AR# 17693

NetGen, Timing Simulation - How do I preserve hierarchy for simulation? How do I create a separate netlist and SDF file for each piece of hierarchy? (KEEP_HIERARCHY)

描述

Keywords: mhf, multiple, hierarchical

Urgency: Standard

General Description:
How do I preserve hierarchy for simulation?

How do I create a separate netlist and SDF file for each piece of hierarchy? (KEEP_HIERARCHY)


As designs increase in size, verification is becoming increasingly more difficult and time consuming. To combat this growing problem, Xilinx has added some new features to the back-end netlist generation tools.

In 5.1i, the ability to preserve hierarchy was added. After preserving hierarchy during Synthesis and using the KEEP_HIERARCHY constraint to preserve the desired hierarchy during implementation, the output simulation netlist will contain the desired hierarchy (a separate VHDL entity or Verilog Module is created for each piece of hierarchy that is maintained). This provides known points within the design where simulation results can be verified.

In 6.1i, the hierarchical netlist feature was expanded by allowing users to create a separate simulation netlist and a separate SDF file for each piece of hierarchy that was maintained. This gives users the ability to perform a "piece-wise" full timing simulation at the design's logical hierarchical boundaries.

This solution explains how to use these features.

解决方案

1

Preserving Hierarchy During Synthesis (Synplify and XST examples below)

Hierarchy must be maintained during Synthesis if you want to generate a hierarchical simulation netlist. If the Synthesis tool flattens the netlist, there is no way for the back-end tools to reconstruct the hierarchy.

Preserving Hierarchy with Synplify

When using Synplify or Synplify Pro, the syn_hier="hard" attribute is used to preserve the hierarchy during synthesis. This should be attached to each piece of hierarchy that you want to be maintained and can be applied in the HDL code. In addition, the KEEP_HIERARCHY constraint must also be applied so that the Xilinx implementation tools will preserve the hierarchy. This can be done in the HDL code as well.

Synplify Verilog example:

Add the "syn_hier" attribute to the module declaration:
module_name (ports) /*synthesis syn_hier="hard"*/;

Attach the "KEEP_HIERARCHY" property to the instantiation of the module:
module_name instance_name(port_mapping) /*synthesis xc_props="KEEP_HIERARCHY=TRUE"*/;

Synplify VHDL example:

Add the "syn_hier" attribute to the Entity declaration:
entity entity_name is
port (ports);
attribute syn_hier : string;
attribute syn_hier of entity_name: entity is "hard";
end entity_name;

Attach the "KEEP_HIERARCHY" property to the instance inside the architecture where component is instantiated:
architecture some_arch of some_entity is
:
attribute xc_props : string;
attribute xc_props of instance_name : label is "KEEP_HIERARCHY=TRUE";
:
begin

Preserving Hierarchy with XST

When using XST, the KEEP_HIERARCHY constraint is used by XST and is automatically passed to the netlist for use by the Implementation tools. There are several ways that the KEEP_HIERARCHY constraint can be applied. These are described below:

Using the KEEP_HIERARCHY switch in XST

In Project Navigator, under the Synthesis Options for XST, there is a Keep Hierarchy option. This is set to "no" by default, but can be switched to "yes" to preserve all hierarchy in the design. When this is turned on, XST will consider each HDL file added to the project as a separate piece of hierarchy and maintain each piece. This is an easy way to preserve the hierarchy in the design, but can preserve too much of the design hierarchy.

It is often better to leave this switch turned Off in XST and apply the KEEP_HIERARCHY constraint in the code to the desired instances. See the examples below:

XST Verilog example - applying KEEP_HIERARCHY to individual instances
Add the keep_hierarchy attribute after the instantiation:
module_name instance_name(port_mapping);//synthesis attribute keep_hierarchy of instance_name is yes

XST VHDL example - applying KEEP_HIERARCHY to individual instances:
Add the keep_hierarchy attribute after the instantiation:
architecture some_arch of some_entity is
:
attribute keep_hierarchy : string;
attribute keep_hierarchy of instance_name: label is "yes";
:
begin

Preserving Hierarchy for a bottom-up Synthesis flow

If you are performing a bottom-up synthesis flow, where separate netlists are created for each piece of hierarchy, you can have the implementation tools automatically attach the KEEP_HIERARCHY constraint to each input netlist:

Project Navigator:
In the Translate properties, turn on "Preserve Hierarchy on Sub Module"
Command Line:
Use the -insert_keep_hierarchy switch on the NGDBuild command line.

NOTE: This option does not have an affect on the design unless multiple netlists are input to the Implementation tools.

2

When and Where to Preserve Hierarchy

To accurately preserve hierarchy during Synthesis and Implementation, certain optimizations must be prevented across hierarchical boundaries. As long as the hierarchical boundaries are well defined (i.e., registered outputs and/or registered inputs between boundaries), preserving hierarchy should not affect the performance of the design. If combinatorial paths exist between two separate pieces of hierarchy and both pieces of hierarchy are selected to be maintained, the performance of the design might be reduced.

To obtain the maximum benefit from the KEEP_HIERARCHY constraint, it should be applied only to blocks in the design whose interface must be visible during the gate-level simulation. These blocks will typically be upper-level blocks in the design that follow good hierarchical design guidelines. By limiting the application of this constraint to selected blocks, the Synthesis and Implementation tools will have more freedom to optimize the design and improve design performance.

Figure 1 below shows an example of how the KEEP_HIERARCHY constraint might be applied to a design.

 Example of how KEEP_HIERARCHY might be applied to a design
Example of how KEEP_HIERARCHY might be applied to a design

3

Preserving Hierarchy During Implementation

As long as hierarchy was preserved during Synthesis and the KEEP_HIERARCHY constraint was attached to the netlist, hierarchy will be maintained during implementation.

NOTE: Make sure that the -ignore_keep_hierarchy option is not turned on in MAP. In Project Navigator, this option is listed in the MAP properties as "Allow Logic Optimization Across Hierarchy." This option is Off by default.

4

Generating a Hierarchical Simulation Netlist

If hierarchy is preserved during implementation, the simulation netlist will contain the desired hierarchy if the NGM file is provided to NetGen (For 5.1i/5.2i, supply the NGM to NGDAnno). The NGM contains all of the hierarchical information preserved by MAP.

Project Navigator:
In the Simulation Model Properties, turn on Correlate Simulation Data to Input Design (this is on by default).

Command Line:
For 6.1i, use the -ngm <ngm_file_name> in NETGEN.
For 5.1/5.2i, the NGM file is supplied at the end of the NGDANNO command line.

The generated simulation netlist should contain a separate VHDL Entity or Verilog Module for each piece of hierarchy that is maintained.

5

Generating Multiple Hierarchical Netlists

In 6.1i, you can generate a separate netlist and a separate SDF file for each piece of hierarchy that was preserved. To do this, you only need to apply the -mhf switch to NetGen and optionally use the -dir switch to create a directory for the simulation netlists and SDF files. An example command line is:
netgen -sim -ofmt {vhdl|verilog} -mhf -ngm design_name_map.ngm -dir directory_name design_name.ncd

In Project Navigator, turn on Generate Multiple Hierarchical Netlist Files in the Simulation Model Properties. In the 6.1i release, there is not a -dir option in the GUI. All of the simulation netlists and SDF files will be placed in the project directory.

NOTE: When the Generate Multiple Hierarchical Netlist option is turned on in Project Navigator, the Use Automatic Do File for ModelSim Simulation is turned off. To simulate through Project Navigator, you need to create your own "do" file. To assist with this, open the "sample_custom.do" file that is created when this option is turned on. After creating your own custom "do" file, turn on Use Custom Do File in the Simulation Properties and select your customer "do" file.
AR# 17693
日期 08/11/2005
状态 Active
Type ??????
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