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AR# 17697

9.1i Constraints - How do you determine I/O locations for Local Clock Routing according to XAPP609?


How do you determine the Data Capture and Transfer clock and data pins outlined in Xilinx Application Note (Xilinx XAPP609): "Local Clocking Resources in Virtex-II Devices"?


Xilinx Application Note XAPP609 outlines two options for Local Clock Routing:

1. Data Capture using IOB Registers only

2. Data Capture and Transfer

The Data Capture and Transfer method has been automated into a Perl script that will tell you the clock and data pin locations for any supported Virtex-II, Virtex-II Pro, and Spartan-3 device in 5.2i sp3.

For information on running the script, use the help menu by typing the name of the script, 'xilperl lrclock.pl'. The Perl script requires a "device.lr" file that is provided with the download.

NOTE: The script excludes VREF, VRP, and VRN pins for both clock and data.



The Perl script in the ZIP file works in 6.3i but not in 7.1i. It is in the process of being updated.

AR# 17697
日期 01/18/2010
状态 Archive
Type 综合文章