UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 17709

9.1i PrimeTime/netgen - Which Xilinx constraints are not supported by PrimeTime flow?

描述

Which Xilinx constraints are not supported by PrimeTime flow?

解决方案

The following conventions are not supported by PCF2SDC: 

 

- Offset translations for DCM (for a multi-DCM clock design) 

- TIMEGRPs with EXCEPT (TIMEGRP <id> = TIMEGRP <id>... EXCEPT TIMEGRP <id>;)  

- MAXDELAY between clock domains  

- Non-PIN constraints  

- TIMEGRPs with rising/falling group qualifiers  

- NET/INSTANCE TIGs with/without Timespec (set_false_path -from -to all elements connected to net)  

- DCM introduced Jitter/Phase-Shift-Errors 

- MAXDELAY PAD-2-PAD with DCM in the path  

- Global Offsets with HIGH/LOW qualifier (Gm)

AR# 17709
日期 05/15/2014
状态 Archive
Type 综合文章
的页面