AR# 17716

6.1i Speed Files - Version 1.116 Virtex-II I/O Modeling Change


Keywords: adjustment, 5.1i

Urgency: Hot

General Description:
The clock-to-out timing parameter and the I/O adjustment numbers have changed in version 1.116 of the Virtex-II speed files. Why have the speed files changed?


The method for testing clock-to-out is the same as in version 1.114 (i.e., 0pF load and 50 Ohm transmission line). The IOB output delays are reduced by an average of 1 ns across the entire device family. The primary reason for this change is the baseline (LVTTL_F12) clock-to-out delay in version 1.114 of the speed files. In addition to the baseline number changes, other IOB adjustment numbers have also changed.

These speed file changes only affect the I/O clock-to-out times and do not affect the I/O setup and hold time values. This model for measuring IOB output delays does not consider the effects of external board loading on the Xilinx device clock-to-out times. For this reason, it is necessary to perform an IBIS model simulation to generate accurate clock-to-out times.

For more information on performing IBIS simulation, see (Xilinx Answer 17720).

Details of Changes in Virtex-II Speed Files Version 1.116:
Approximately 1 ns improvement in output delay for all I/O standards, without capacitive load.

Description of the I/O Adjustment Issue in Version 1.113, 1.114 and 1.116:
- V1.113 was based on output delays at 35pF load.
- V1.114 was based on a 50 Ohm transmission line model, but contained inconsistent data. The I/O adjustments were correct, and baseline was still 35pF.
- V1.116 was created to address the above inconsistency; I/O adjustments are unchanged, and the reference baseline is reduced by 1 ns to correct for loading.

Impact on Designs:
- Neither the silicon nor the test procedures at production have changed; the change is simply a shift in the location where the delay is allocated.
- Output delays are affected, but Setup/Hold times did not change.
- Smaller I/O numbers are received from TRCE.
- It is now very important to account for the board loading; IBIS simulators or equivalent must be used. For more information, see:

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AR# 17716
日期 03/27/2007
状态 Archive
Type 综合文章