AR# 17721: Virtex-II/Pro - What is the Internal Configuration Access Port (ICAP)?
Virtex-II/Pro - What is the Internal Configuration Access Port (ICAP)?
Keywords: Virtex-II, partial, SelectMAP, ICAP, internal, configuration, access, port, pro
General Description: What is the Internal Configuration Access Port (ICAP)?
ICAP is a configuration method that is available to the internal logic resources after the device is configured. The ICAP block exists in the lower-right corner of the array and emulates the SelectMAP configuration protocol.
See the library's guide for instantiation template.
Inputs The input pins to the ICAP are as follows: /ENABLE - Port enable for write/read with programmable input inversion Active low. /WRITE - Allow writing/reading to configuration port (write=1,read=0) with programmable input inversion. Active low. CCLK - Configuration Clock DI[7:0] - Data Input bus
Outputs The output pins of the ICAP are as follows: DO[7:0] - Data Output bus BUSY - Same as SelectMAP
Usage This feature allows partial reconfiguration. Internal access to the configuration logic allows the creation of "IRL Boot Cores" by partially reconfiguring the FPGA. An "IRL Boot Core" bootstraps the FPGA from a smaller SPROM with a communication interface such as USB, Ethernet, PCI, PCI-X, etc. The WorkHorse design is then loaded through the communication interface and into the ICAP block. Once the design is completely loaded, it operates normally and interacts with the WorkHorse design through a FBCC (Fixed Bus Communicator Core). The process is as follows:
1. Load IRL Boot Core from SPROM (Master SelectMAP, Master Serial): - Communication Interface PCI, PCI-X, USB, Ethernet, Radio, ATM, etc. - ICAP block - Fixed Bus Communicator Core - Not reconfigured through ICAP 2. Establish communications. 3. Load the WorkHorse design through ICAP. 4. Disable ICAP until next re-load. 5. Communicate to WorkHorse through FBCC until further notice.
Using the ICAP with a IRL Boot Core relies on the premise that the IRL Boot Core surrounds the ICAP block, CLBs, IOBs, and Block SelectRAMs, and is not reconfigured. The WorkHorse design does not require any use of resources within the resource space of the IRL Boot Core (long lines, hexes) beyond the shared and fixed resources in the FBCC.