When I run timing analysis on a design that uses an OFFSET IN constraint, clock phase information is not used in the calculation or analysis for holds.
When I add the VALID keyword to the OFFSET IN constraint, the clock phase information is used in the calculation or analysis.
OFFSET IN constraints should include the clock phase information whether or not the VALID keyword is used. For correct analysis, Xilinx recommends that you include the VALID keyword in the OFFSET IN constraints.
This problem has been fixed in the latest 6.1i Service Pack, available at:
The first service pack containing the fix is 6.1i Service Pack 2.