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AR# 17941

6.1i PACE - Edge constraints are not seen as valid LOC constraints

描述

Keywords: valid, lock, LOC, constraints, edge

Urgency: Standard

General Description:
When I try to lock a bus or signal to an edge, the DRC does not allow me to do this.

解决方案

This problem has been fixed in the latest 6.1i Service Pack, available at:
http://support.xilinx.com/support/techsup/sw_updates
The first service pack containing the fix is 6.1i Service Pack 1.
AR# 17941
日期 03/27/2007
状态 Archive
Type 综合文章
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