AR# 17955

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6.1i ECS - A Verilog keyword is misspelled Verilog as "inital" in a test fixture generated by SCH2Verilog

描述

Keywords: schematic, Verilog, test fixture

Urgency: Standard

General Description:
The Verilog test fixture generated for a schematic source contains a spelling error ("inital" should be spelled as "initial"), and this error prevents the test fixture from compiling in MXE. The error is as follows:

// Initialize Inputs
`ifdef auto_init
inital begin

解决方案

This problem has been fixed in the latest 6.1i Service Pack, available at:
http://support.xilinx.com/support/techsup/sw_updates
The first service pack containing the fix is 6.1i Service Pack 1.
AR# 17955
日期 01/08/2006
状态 Archive
Type 综合文章
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