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AR# 17978

6.1i ISE - Synplicity will not automatically find Dual Edge Trigger (DET) instantiated components for CoolRunner-II designs


Keywords: CoolRunner, DET, Synplicity, Synplify, Dual Edge Trigger, DET, VHDL, CR

Urgency: Standard

General Description:
When Project Navigator calls Synplicity to synthesize a CoolRunner-II VHDL design, the cpld_sim library is not passed. This prevents Synplicity from recognizing Dual Edge Trigger (DET) components that might have been instantiated in the design.


To make this flow work, add "cpld_det.vhd" (found in "%Xilinx\VHDL\src\ISE\cpld") to the project, set it as a library (cpld_sim, not work), and then in the VHDL source add:

library cpld_sim;

use cpld_sim.CPLD_DET_COMPONENTS.all;

This problem has been fixed in the latest 6.1i Service Pack available at:
The first service pack containing the fix is 6.1i Service Pack 1.
AR# 17978
日期 02/07/2006
状态 Archive
Type 综合文章