We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 18084

Virtex-II/Virtex-II Pro Configuration - Maximum CCLK and Startup Clock Frequencies


Keywords: CCLK, startup, clock, UserCLK, user, clk, configuration, serial, selectmap, select, map, frequency, frequencies, jtag

Urgency: Standard

Problem Description:
The Virtex-II and Virtex-II Pro User Guides misrepresent the maximum frequency for CCLK. Furthermore, they contain no information on the maximum frequency of the Startup Clock.


As the device receives configuration data, a processing unit parses the data, places it on the configuration bus, and directs the data to the correct configuration locations. The maximum frequency for the processing unit and bus is 50MHz. Because the processing unit and bus are clocked by CCLK during configuration and then by the Startup Clock (which is user-selectable to be CCLK, JTAGClk, or UserCLK) during the startup sequence, the maximum frequency of CCLK and the Startup Clock is 50MHz.

If SelectMAP mode, CCLK can be run at a maximum speed of 50MHz with or without handshaking. The V2 user guide will be updated to document this limitation.
AR# 18084
日期 10/01/2008
状态 Archive
Type 综合文章