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AR# 18146

6.1 / 3.2 EDK - Timing constraints for DCR bus

描述

Keywords: EDK, DCR, PPC, PowerPC, Timing

Urgency: Standard

General Description:
I am using the DCR bus in my design. What timing constraints should I use?

解决方案

The following documentation provides an overview of the timing constraints associated with the DCR bus:

http://www.xilinx.com/txpatches/pub/documentation/misc/ppc_dcr_timingguide.pdf
AR# 18146
日期 03/07/2006
状态 Archive
Type 综合文章
的页面