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AR# 1825

** OBSOLETE ** 2.1i UNISIMS, SIMPRIMS - CLKDLL doesn't lock after RST is de-asserted

Description

Keywords: Verilog, CLKDLL, LOCK

Urgency: Standard

General Description:
In the 2.1i UNISIMS/SIMPRIMS Verilog models, there is a bug
in the CLKDLL and CLKDLLHF models in which the LOCKED
signal never locks after the RST signal is de-asserted.

解决方案

This is fixed in Alliance 2.1i sp3 available at:
http://support.xilinx.com/support/techsup/sw_updates
AR# 1825
创建日期 08/31/2007
Last Updated 08/28/2002
状态 Archive
Type ??????