XtremeDSP Development Kit - Where can I find information on the clocking available for the XtremeDSP Development Kit?
This information can be found in the XtremeDSP Development Kit Documentation.
The page numbers are based on the following release of the XtremeDSP Kit Development Documentation:
"NT107-0132 - XtremeDSP Dev Kit User Guide Issue 9.pdf"
There is a programmable clock in the BenONE motherboard.
Page -- 40 Section 5.8 This section covers all of the available clock sources, and gives a list of the programmable clock frequencies.
This is the clock that is used by the Hardware Co-Sim with the XtremeDSP Development Kit.
System Generator Uses the Programmable Clock, and will round the frequency that you entered to the nearest available programmable clock frequency.
Please see (Xilinx Answer 18281) for more information about using the clocking of the XtremeDSP Development Kit when doing Hardware Co-Sim.
There is also a socket on the BenONE motherboard where fixed oscillator can be placed.
Page -- 39 Section 5.6
Please see (Xilinx Answer 18072) for more information on the recommended Oscillator.
There is a fixed oscillator on the BenADDA daughterboard.
The fixed oscillator on the BenADDA daughterboard is a 65MHz oscillator.
Clocking the DACs and ADCs
The BenADDA also has a Virtex-II XC2V80 FPGA that is used for clock management of the DACs and ADCs.
Page -- 65 Figure 32 shows that there is an fixed oscillator or and external clock and an internal clock or a clock from the User FPGA that can be used with the XtremeDSP Development Kit.
Page -- 82 Figure 37 shows the use of the Onboard fixed oscillator feeding the Clock FPGA, which then feeds the 2 DACs, 2 ADCs, and the User FPGA.
Page -- 101-102 Section 10.3.2 explains how to use the internal PLL for the two AD9772A DACs.
Page -- 110 Section 10.5.3 explains the clocking for the ADCs.
Page --111-115 Gives details on the User FPGA clocking management.
The BenADDA is supplied with various bit files. The user is simply required to choose the Clocking option most suited to the end application.
Page -- 111 Figure 67 gives an overview diagram of the User FPGA clocking inputs and outputs.