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AR# 18362

7.1i XST - "ERROR:HDLCompilers:44 - <file>.v line xx Illegal left hand side of blocking assignment"

描述

Keywords: 247, Verilog, synthesize

Urgency: Standard

General Description:
When synthesizing a Verilog design, the following errors might occur:

"ERROR:HDLCompilers:247 - <file>.v line xx Reference to scalar wire '<signal>' is not a legal reg or variable lvalue"
"ERROR:HDLCompilers:44 - <file>.v line xx Illegal left hand side of blocking assignment"

解决方案

These errors will occur if signals declared as wire type are assigned a value using an always block statement, like this:

<code>
...
wire data;
always@(<condition>)
data = din;
...
</code>

If a conditional assignment is desired, a reg data type must be used.
AR# 18362
日期 01/06/2009
状态 Archive
Type 综合文章
的页面