While implementing a design, an error message similar to the following occurs:
"ERROR:Cpld:6 - Cannot assign Output Pin <my_signal> to Pin X (FBy_z). This pin does not support the functionality of that signal."
This can occur if you are attempting to pin lock an I/O to a JTAG pin but have forgotten to turn off the "Reserve ISP Pins" option. That option is ON by default, meaning that the JTAG pins are dedicated for JTAG use only.
To be certain whether the JTAG pins have been reserved, open the JEDEC file in a text editor and look for "Note ISP bit *" near the bottom of the file. The value of the ISP bit is indicated by the last digit in that line.
If the ISP bit is 1, then the ISP pins have been reserved.
If the ISP bit is 0, then the ISP pins are available for use as I/O.
Note ISP bit *
The last digit in the second line denotes that the JTAG pins HAVE been reserved in this case.
For information on using JTAG pins as I/O using the Port Enable pin, see (Xilinx Answer 8455).