AR# 1840


Foundation XVHDL: Setting NODELAY property on inputs


Keywords: foundation xvhdl nodelay attribute

Versions: F6.x, F1.3/F1.4

Urgency: standard

General Description:

The NODELAY attribute applies to XC4000E/EX/XL and XC5200
families. By default, IOB flip-flops in the XC4000 (or CLB
flip-flops using direct connects from the IOB for the XC5200)
have an input delay which results in zero external hold time
on the input data path. This delay may be removed by placing
the NODELAY attribute on the inputs. This will result in a
smaller setup time, but a positive hold time.

Below is an example of how to add the NODELAY attribute using
Foundation XVHDL.

**Please note that this solution applies only to the Foundation
XVHDL compiler. If you are using the Express compiler, you
may specify the NODELAY property in the Express Constraints


--Example of using NODELAY parameter

library IEEE;
use IEEE.std_logic_1164.all;

entity input_nodelay is
port (DIN, CLOCK: in std_logic; DOUT: out std_logic);
attribute NODELAY: boolean;
attribute NODELAY of DIN: signal is true;
end input_nodelay;

architecture behv of input_nodelay is

process (CLOCK)
if CLOCK'event and CLOCK='1' then
end if;
end process;
end behv;
AR# 1840
日期 01/02/2000
状态 Archive
Type 综合文章
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