AR# 18423

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LogiCORE Asynchronous FIFO v5.1 - Why are the Verilog simulation model almost empty and almost full flags not synchronous to RD_CLK?

描述

Why are the Verilog simulation model almost empty and almost full flags not synchronous to RD_CLK?

解决方案

The EMPTY and ALMOST_EMPTY flags are supposed to be synchronous to RD_CLK, and the FULL and ALMOST_FULL flags are supposed to be synchronous to the WR_CLK. However, these flags all trigger on: 

@(posedge wr_pulse or posedge rd_pulse or posedge AINIT) 

 

As a result, these flags are switching on both RD_CLK and WR_CLK. For example, the EMPTY flag is asserted on the RD_CLK, and deasserted on the WR_CLK.

AR# 18423
日期 05/16/2014
状态 Archive
Type 综合文章
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