To specify the initial power-up state of a flip-flop in a CPLD (XC7300 or XC9500), you must attach an INIT property to the flip-flop. The default power-up state, if no INIT property exists, is zero (logic low).
NOTE: This does not apply to Xilinx FPGAs.
In the Mentor Schematic, select the flip-flop whose initial state you want to change, then right-click and select Button -> Properties -> Add from the menu.
Add the following properties:
Property Name: =INIT
Property Value: S (initial set state) or R (initial reset state)
The equal sign before the INIT property name is required (without it, the property will not properly pass through EDIF2XNF).