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AR# 18442

6.1i Virtex-II PAR - Clock placement fails with invalid error about conflicting IN0 and IN1 pin usage on BUFGMUX's


Keywords: ERROR:Place:37, BUFGMUX, IN0, IN1, conflict, placer, placement

Urgency: Hot

General Description:
Cases have been seen where designs failed during the clock placement phase with an error message indicating that there is a conflict in pin usage between neighboring BUFGMUX's which share a routing resource:

"ERROR:Place:37 - A global clock component <CLK_GEN/PORT12_BUFGMUX> configured as
a selectable mux is placed in site BUFGMUX2S. This configuration requires that the global clock
site BUFGMUX2S either be empty or contain a global buffer or mux with the inputs IN0 and IN1
either not drive by a signal or driven by the same signals as the original muxes IN1 and IN0 pins
respectively in order to route up both of the inputs. In other words the input signal for IN0 on one
buffer must be the same as the input signal driving IN1 on the other buffer (or one of them must not
be driven) to place the two buffers in the paired sites. The site BUFGMUX2S has the global buffer
<CLK_GEN/PORT12_BUFGMUX> placed there. This design is unroutable. Please correct this
problem before continuing."

It has been determined that this is an invalid error that occurs when the clock placer attempts to place a design that has an input net driving three or more BUFGMUX IN0/IN1 pins.


This problem is scheduled to be fixed in 6.2i. Meanwhile, the work-around is to lock the placement of all BUFGMUX's, DCMs and Clock IO and set the following environment variable to skip the autoplacement of these components:

Solaris and Linux


For more general information about setting ISE environment variables, see (Xilinx Answer 11630).
AR# 18442
日期 10/19/2008
状态 Archive
Type 综合文章