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AR# 18461

6.1 EDK Clock signals on multi-clock signals are connected to same clock if unspecified in the MHS

描述

Keywords: PLB2OPB, bridge, clock, PlatGen, EDK, MHS

Urgency: Hot

General Description:
When upgrading to 6.1 from 3.2, clock signals on multi-clock signals are connected to the same clock if unspecified in the MHS.

If the PLB Clock != OPB Clock, then all OPB accesses will fail.

解决方案

To work around this issue, you can explicitly connect the bridge clock signals in the MHS as follows:

BEGIN plb2opb_bridge
PARAMETER INSTANCE = plb2opb
...
PORT PLB_Clk = plb_clock
PORT OPB_Clk = opb_clock
...
END

This problem only affects designs migrating to 6.1 from 3.2. This has been fixed in 6.2.
AR# 18461
日期 04/09/2007
状态 Archive
Type 综合文章
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