We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 18672

LogiCORE Direct Digital Synthesis (DDS) 4.2 - How do you specify output width in DDS 4.2?


In DDS 4.1, the user could specify the output bit widths. How can I do this with the DDS v4.2?


The output width can be changed by altering the dB and Clock Frequency. The disadvantage is that the input page for the dB and Clock Frequency is several tabs away from the output bit width displayed.

AR# 18672
日期 05/16/2014
状态 Archive
Type 综合文章