AR# 18673


6.1i XST - Incorrect logic generated when using the conv_std_logic_vector function on a signed integer


Keywords: XST, VHDL, function, package, IEEE, conversion, sign, bit, signed

Urgency: Standard

General Description:
When using the conv_std_logic_vector VHDL function to convert a signed integer to a std_logic_vector, XST does not sign extend the sign bit.


Unfortunately, there is no work-around available for the signed integers/vectors. The only solution is to avoid signed integers/vectors.

This issue is fixed in the latest 6.2i Service Pack, available at:
The first service pack containing the fix is 6.2i Service Pack 2.
AR# 18673
日期 03/07/2006
状态 Archive
Type 综合文章
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