We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 18721

6.1i Timing Analyzer/TRCE - Tools incorrectly report Reset path on "n" side only for OFFSET/OUT of differential output (Tiosrdo)


General Description:

In my design with a differential output registered inside of the IOB, the OFFSET/OUT constraint is analyzing incorrect paths. The longest path on the "n" side is shown to be from the reset flop through the "n" side data FF to the output pad (reg_sr_q is not enabled). This path is not reported for the "p" side, and should not be reported for the "n" side.


This issue affects all Virtex-II families (Virtex-II, Virtex-II Pro, and Spartan-3). The tools have been modified to contain a new timing parameter named "Tiosrdo" to describe these paths and allow TRCE/Timing Analyzer to filter out these specialized paths. The first release containing this fix is 6.2i, scheduled for February 2004.

AR# 18721
日期 01/18/2010
状态 Archive
Type 综合文章