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AR# 18769

6.2 / 6.1 EDK/SimGen - SimGen produces incorrect "system_init.v" file for Verilog simulations


Keywords: XPS

Urgency: Standard

General Description:
Verilog simulations fail due to incorrect defparam statements in the "system_init.v" file generated by SimGen; this results in errors such as the following:

"# Loading work.system_conf
# ** Error: (vsim-3043) system_init.v(9): Unresolved reference to 'system' in system.bram.bram.ramb4_s8_s8_0.INIT_00.
# Region: /system_conf"

For example, a "system_init.v" file looks similar to the following:

module system_conf;

defparam system.bram.bram.ramb4_s8_s8_0.INIT_00 = 256'h20D920B82080B920B9202080B9F4F4C4D820F4F4C4D820202021B8B0B8B080B8;

This assumes that "system" is the top-level of the simulation hierarchy in the testbench. The current "system_init.v" cannot be used since there is no top-level "system" instance. Also, if a testbench is used, EDK currently does not have a way to specify a testbench name other than "system".

Also, for structural simulations, this is a problem because XST flattens the netlist by default. When the Verilog file is generated for the design, the hierarchy is lost and does not match what is listed in the "system_init.v" file.


To work around this issue, use a testbench that instantiates the system as "system", and when you perform structural simulations, maintain the hierarchy.
AR# 18769
日期 03/08/2006
状态 Archive
Type 综合文章