AR# 18874: 6.2i NetGen, UltraController - Timing values in the SDF are set to "0", which causes the failure of the Verilog Timing Simulation for the UltraController
6.2i NetGen, UltraController - Timing values in the SDF are set to "0", which causes the failure of the Verilog Timing Simulation for the UltraController
Keywords: NetGen, UltraController, Verilog, SDF, all, 0, zero, timing, simulation, no, delay, keep, hierarchy
General Description: In 6.2i, the SDF values are set to "0" when preserving hierarchy, which causes the failure of the Verilog Timing Simulation for the UltraController.
Another way to work around this problem is to not preserve the hierarchy. This avoids the bug in NetGen, and the SDF is populated with the correct values. The drawback of this work-around is that the simulation netlist is flattened and the Waveform DO files provided with the UltraController Demo will no longer work. The DO files reference the names of the signals as they are in the simulation netlist where hierarchy is preserved.
To not preserve hierarchy in ISE, disable the Simulation Model Property to Correlate Simulation Data to Input Design. This prevents the maintenance of the hierarchy, but the SDF will be populated with the correct values.
If you are running NetGen from the command line, remove the "-ngm" command line switch to work around this problem.
You can also work around this problem by disabling SDF annotation as follows: 1. In Project Navigator, right-click "Simulation Post-Place & Route Verilog Model", and select "Properties". 2. Select the Simulation Model Properties tab. 3. In Other NetGen Command Line Options, enter: -sdf_anno false
If "Other NetGen Command Line Options" is not displayed, go to Edit -> Preferences -> Processes, and select Advanced instead of Standard.
By disabling the SDF annotation, the SDF file is not used, and the default unit delays in the SimPrim models are used. This shows that the functionality is correct, but the true timing delays are not incorporated.