AR# 18877


14.x Timing Analyzer/Constraint - Using a FF (gate clock) for divide circuitry causes problems with the PERIOD analysis


I want to obtain a divided version of my clock by using logic inside the device, so I use a flip-flop to divide down the clock. I then put a new PERIOD constraint on the output of the flip-flop. However, when I do this, strange behavior occurs:

1. Some of the paths that should be covered by my new PERIOD constraint are being analyzed under my original PERIOD constraint. (If I change the order of the PERIOD constraints in the analysis, the problem is corrected.)
2. Certain clock arrival times are incorrect for the different rising/falling edges.


Xilinx recommends always using a DCM/DLL/PLL to perform clock division inside the FPGA. Using a flip-flop for this causes the divided clock to be on local routing; it is then difficult to obtain an accurate analysis between any cross-clock domain paths due to an unknown relationship between the two clocks caused by skew.

However, it is possible to "gate" the clock for division. The problems occur because the flip-flop used for division is in both time groups (the original clock and the newly divided clock). Use the following constraints in the UCF to fix this:

# PERIOD constraint on the original PAD clock:
NET "clk" TNM_NET = "clk";
TIMESPEC TS_clk = PERIOD "clk" 10 ns;
# Put the flip-flop used for the clock divide in its own group:
INST "clk_div_ff" TNM = "clk_div_ff";
# Create a group containing all the elements fed by the new divided clock:
NET "clk_div" TNM_NET = "clk_div_temp";
# Create a new group that contains all the elements fed by the new divided clock except the actual flip-flop used for division, and use that flip-flop in the PERIOD constraint:
TIMEGRP "clk_div" = "clk_div_temp" EXCEPT "clk_div_ff";
TIMESPEC TS_clk_div = PERIOD "clk_div" 20 ns;

AR# 18877
日期 12/15/2012
状态 Active
Type 综合文章
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